Re: gEDA-user: Split ground planes and zero ohm jumpers

[Thomas Oldbury <toldbury@xxxxxxxxx>]

   Out of curiosity, how do other PCB layout products (Altium, Orcad,
   etc.) implement this? Follow by example?

   On 7 April 2011 18:21, Stephan Boettcher
   <[1]boettcher@xxxxxxxxxxxxxxxxxx> wrote:

   John Griessen <[2]john@xxxxxxxxxxxxxx> writes:

   > On 04/07/2011 04:52 AM, Stephan Boettcher wrote:
   >> PCB layer groups may be used here.  Put the short on an extra layer,
   in
   >> an extra group.  At checkout time, you can assign the extra layer to
   the
   >> group representing the copper layer that needs shorting.  This is
   >> probably a single char in the PCB file header, and can be done with
   a
   >> simple sed script.
   >
   > I like that idea -- at least until someone figures how to have a
   starpoint
   > symbol and footprint that keeps DRC checking of separate ground
   planes while
   > still having a short there for fabbing purposes.
   >
   > I'm thinking of two scripts external to pcb, for use with make.
   While editing
   > a pcb board, I would run DRC and effectively have a non conductive
   piece
   > of trace between separately named ground planes.  When I run make
   faboutput,
   > one script is run to change the non conductive piece
   > of trace to copper on a layer, then output RS274-X, the run the other
   script
   > to change the piece of copper on a layer to a non conductive piece
   > of trace.
   >
   > We don't have the concept of non-conductive built into pcb now
   though,
   > so some kind of "ignore for DRC purposes" might do.
   >
   > There's still a problem with that method though... It won't check for
   > proper clearances of the starpoint blob of copper to other copper if
   it
   > is handled by an "ignore for DRC purposes" attribute.

     As soon as we have the option to define arbitary layer types, we
     also
     need to be able to define arbitrary DRC rules.  The star-point may
     be a
     footprint with a structure on some non-conductive "shorts" layer,
     which
     will need to be accompanied by a set of design rules in the
     technology
     specs.  The fact that the non-conductive "shorts" layer is
     implemented
     in conductive copper by merging the layer with the bottom copper is
     irrelevant, since for netlist purposes it is non-conductive, just
     like a
     "resistor" layer.  Part of the design-rule check is to be perfomed
     manually, you'll always need to check your footprints in your
     library.
     --
     Stephan

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References

   1. mailto:boettcher@xxxxxxxxxxxxxxxxxx
   2. mailto:john@xxxxxxxxxxxxxx
   3. mailto:geda-user@xxxxxxxxxxxxxx
   4. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user


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