Re: gEDA-user: Icarus Verilog: FPGA-like automatic initialized registers?

[Ales Hvezda <ahvezda@seul.org>]

[ Ales here, I'm reposting this since majordomo didn't recognize the
  e-mail as being subscribed to the geda-dev/user mailinglist.  Please note
  that I am not the original author. ]

-- Cut here --
From: Tommy Thorn <Tommy@numba-tu.com>

Thanks to both Stephen and Alexander for the rapid response.

On Sunday 10 August 2003 11:40, Stephen Williams wrote:
...
> > or simulation specific initialization
> >
> >   ....
> >   initial
> >   begin
> >     for (...)
> >        reg[$i] = 0;
> >
> >   (I'm sloppy on the syntax here).
>
> In Icarus Verilog, and most modern simulators, you can use declarations
> like so:
>
>      reg foo = 0;
>
> This gets your variables initialized as you want them. Furthermore,
> many of the FPGA *synthesizers* (including Xilinx xst) let you use
> that syntax to specifiy the INIT value for the FF.

Yes, but doesn't this only work for scalar registers?  My problem is mostly 
with arrays.  Also, I'm pretty sure that the synthesizer I tried it on 
(Quartus II?) just ignored this kind of initialization.  Though it would be 
the next best thing if I could get it to work for arrays.

If I Understand Correctly, I can't initialize the array in an initial block 
because the array lives in a sub-module.


On Sunday 10 August 2003 11:41, Alexander Perry wrote:
> This doesn't answer your question, since I don't know of one, but
> it is generally a good idea to write the explicit initialization
> (a) so you can migrate the design to ASIC at a future time,
> (b) some CPLDs have defaulted registers boot up to all '1',
> (c) the formalism has helped me to find hidden bugs and stuff,
> (d) most of my FPGA designs have a software reset pin anyway,
> (e) relying on a nonstandard feature leads to nonportable code.
> For a lot of industrial uses, (d) is a critical factor because
> ram-based FPGAs take a long time to boot.  Often much longer than
> you can afford to wait when just seeking to do a subsystem reset.

These are all good points, but given my design will always be FPGA specific, 
(a) and (b) doesn't apply.  (e) is true in general, but all I was looking for 
was for the simulation to be more faithful to the reality.  The reality is 
that for SRAM based FPGAs, the registers *are* defined upon boot.  From a 
synthesis point of view, the code did not change or become less portable 
(amoung SRAM based FPGAs).  From a synthesis point of view, the code did not 
change or become less portable (amoung SRAM based FPGAs).  

If I could find a not too intrusive way to tell Icarus the initial values of 
registers, then that would be acceptable (again, arrays are the main 
problem).

Thanks,

  Tommy