Re: gEDA-user: Icarus Verilog: FPGA-like automatic initialized registers?

[Alexander Perry <alex.perry@qm.com>]

geda@meko.dk wrote:
> So the question is: is there a simple switch to the Icarus Verilog
> simulator which will make it let all registers come up initialized to
> zero, just like an FPGA?

This doesn't answer your question, since I don't know of one, but
it is generally a good idea to write the explicit initialization
(a) so you can migrate the design to ASIC at a future time,
(b) some CPLDs have defaulted registers boot up to all '1',
(c) the formalism has helped me to find hidden bugs and stuff,
(d) most of my FPGA designs have a software reset pin anyway,
(e) relying on a nonstandard feature leads to nonportable code.
For a lot of industrial uses, (d) is a critical factor because
ram-based FPGAs take a long time to boot.  Often much longer than
you can afford to wait when just seeking to do a subsystem reset.