[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]

Re: gEDA-user: Icarus Verilog: FPGA-like automatic initialized registers?

Tommy Thorn wrote:

Thanks to both Stephen and Alexander for the rapid response.

On Sunday 10 August 2003 11:40, Stephen Williams wrote:
...


or simulation specific initialization

 ....
 initial
 begin
   for (...)
      reg[$i] = 0;

 (I'm sloppy on the syntax here).

In Icarus Verilog, and most modern simulators, you can use declarations
like so:

    reg foo = 0;

This gets your variables initialized as you want them. Furthermore,
many of the FPGA *synthesizers* (including Xilinx xst) let you use
that syntax to specifiy the INIT value for the FF.

Yes, but doesn't this only work for scalar registers? My problem is mostly with arrays. Also, I'm pretty sure that the synthesizer I tried it on (Quartus II?) just ignored this kind of initialization. Though it would be the next best thing if I could get it to work for arrays.

If I Understand Correctly, I can't initialize the array in an initial block because the array lives in a sub-module.
You can initialize arrays and vectors this way, you cannot initialize
memories this way. SystemVerilog (and some talk in post -2001 Verilog)
attempt to address this for arbitrary arrays, but that doesn't count
for the immediate real world.

If Quartus II ignored it, then it just doesn't support it. For the
record, Icarus Verilog -tfpga currently does not generate the INIT=
properties either, but that is the correct way to express what you
want, so both QuartusII and Icarus Verilog have a bug there.

(Icarus Verilog *simulates* initializations perfectly well. It is the
synthesizer that lacks.)
--
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."