gEDA-user: Icarus Verilog: FPGA-like automatic initialized registers?

[geda@meko.dk]

I'm a Verilog, but I've tried researching this question in vain, so I
turn to this forum.

In standard Verilog, registers start out in the unknown (x) state, and
initialization either requires explicit reset logic, eg.

....

  always @(posedge clk)
    if (~reset_n) begin
      pc <= 32'h0000;
      ....
    end else begin
      // Normal path here

or simulation specific initialization

  ....
  initial
  begin
    for (...)
       reg[$i] = 0;

  (I'm sloppy on the syntax here).

Both approaches becomes rather awkward with non-trivial arrays and in
the explicit reset case can hurt designs that doesn't need anything
but the default reset-on-power-on provided by all FPGAs.

So the question is: is there a simple switch to the Icarus Verilog
simulator which will make it let all registers come up initialized to
zero, just like an FPGA?

Thanks!

/Tommy