geda@meko.dk wrote:
I'm a Verilog, but I've tried researching this question in vain, so I
turn to this forum.
In standard Verilog, registers start out in the unknown (x) state, and
initialization either requires explicit reset logic, eg.
....
always @(posedge clk)
if (~reset_n) begin
pc <= 32'h0000;
....
end else begin
// Normal path here
or simulation specific initialization
....
initial
begin
for (...)
reg[$i] = 0;
(I'm sloppy on the syntax here).
In Icarus Verilog, and most modern simulators, you can use declarations
like so:
reg foo = 0;
This gets your variables initialized as you want them. Furthermore,
many of the FPGA *synthesizers* (including Xilinx xst) let you use
that syntax to specifiy the INIT value for the FF.
--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."