gEDA-user: iVerilog -tfpga: "Asynch if missing else" error not quite fixed

[Mike Butts <mbutts@realizer.com>]

Hi Stephen,

That "Asynchronous if statement is missing the else clause."
error still crops up if there are multiple assignments.  Here's a clip
from my design (also attached) that repeats the bug:

module dffx (ir, stall, ce, reset, clk, last_ir, was_stall);
	input [15:0] ir;
	input stall, ce, reset, clk;
	output [15:0] last_ir;
	output was_stall;
    reg [15:0] last_ir;
    reg was_stall;
    always @(posedge clk) begin
        if (reset) begin
            last_ir <= 0;
            was_stall <= 0;
        end
        else if (ce) begin
            last_ir <= ir;
            was_stall <= stall;
        end
    end
endmodule

Now I'm running the 20030810 snapshot that you packaged as an rpm, thanks,
which does indeed handle my previous example correctly, on Mandrake 8.2.

I often use this style to bundle all the flops and registers that share a 
common
clock, reset and enable, to be more concise.

Thanks again for your help.

  --Mike
module dffx (ir, stall, ce, reset, clk, last_ir, was_stall);
	input [15:0] ir;
	input stall, ce, reset, clk;
	output [15:0] last_ir;
	output was_stall;
	
    reg [15:0] last_ir;
    reg was_stall;
    always @(posedge clk) begin
        if (reset) begin
            last_ir <= 0; 
            was_stall <= 0; 
        end
        else if (ce) begin
            last_ir <= ir;
            was_stall <= stall;
        end
    end
endmodule