gEDA-user: Re: What is the problem with this benchmark test case?

["CN" <mis4@xxxxxxxxxxx>]

OK, I reduced the test to almost nothing and here the code that gives the same error:

-------------------------------------
//prep3logic.v   3 bit case test

module prep3logic ( state, next_state);

  input  [2:0] state ;
  output [2:0] next_state ;
  reg [2:0] next_state ;
  
  always @ (  state ) begin
    case (state)
      0:
          next_state = 1 ;
      1:
         next_state = 3 ;
      2:
          next_state = 2 ;
      3:
          next_state = 0 ;
      4:
          next_state = 1 ;
      5:
        next_state = 3 ;
      6:
          next_state = 2 ;
      7:
          next_state = 0 ;
    endcase
  end
endmodule
------------------------------

When I change the line   input  [2:0] state ;
to   input  [1:0] state ;

there is no error.  So it seems now there is a limitation of maximum of only 4 cases allowed.   Somebody please let me know where in the source code this problem might be!

Cordially, CN



On Fri, 05 Aug 2005 13:29:07 -0700, CN wrote:

Hello All,

When I run the attched source prep3.v (it is an old, very small state machine benchmark test)  thru ivl v0.8.1,  with -tfpga -parch=virtex

I get something like:

Assertion failed: ivl_lpm_selects(net) == 1, file xilinx.c, line 718

Is there a problem with this test case?  Anybody has any suggestions as to how I might modify ivl to run this?  I am willing to do the work, if some guidance can be given.  Thank you for the help!

Cordially, CN