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Re: gEDA-user: Icarus Verilog info?

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Subject: Re: gEDA-user: Icarus Verilog info?
From: gene <carzrgr8@xxxxxxxxxxxxx>
Date: Mon, 08 Aug 2005 05:42:40 -0400
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In the original example, DataRcd and corr will all be registers (flip-flops), which will all be correct on the same cycle.

Maybe it will synthesize properly, but I don't think it will simulate correctly at the functional level. I sort of like it when functional simulation matches with post synthesis/place-route simulation. I will verify this today at work, and post back to the list :-)


gene

References:
- gEDA-user: Icarus Verilog info?
  - From: Harold D. Skank
- Re: gEDA-user: Icarus Verilog info?
  - From: gene
- Re: gEDA-user: Icarus Verilog info?
  - From: Udi Finkelstein

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