People, I'm using Icarus Verilog as a front end to some Lattice tools. Basically I have two questions, an immediate procedural question, then a longer term question regarding how to write some ancillary programs. The procedural question: I've attached the programs I'm currently attempting to run. When I call the ./vlogTST program (also attached) I get the following output on the control console. Please ignore the syntax error info associated with v:37, I know about that and will eventually get it corrected. What I don't understand is what the v:51: message is trying to tell me. [designer@AMD RcvAlg]$ ./vlogTST /home/designer/Etrema/RcvAlg/testfixture.v:37: syntax error /home/designer/Etrema/RcvAlg/testfixture.v:37: error: malformed statement testfixture.v:37: syntax error testfixture.v:37: error: malformed statement testfixture.v:51: Module testfixture was already declared here: /home/designer/Etrema/RcvAlg/testfixture.v:14 For the second question, the old iverilog-fpga man page (apparently older than the current iverilog man page) referring to the parch=lpm option indicates that users may write interface libraries to connect netlists to vendor architecture. I'm using Lattice devices, and have to go through an involved procedure to get from the behavioral code to the EDIF model acceptable to my Lattice compiler. First of all, is this possibility (writing the interface library) still available, and if so, could you give me some clues about how to start? Thank you for your consideration. Harold Skank
/* Author.......H. Skank */
`timescale 10ns / 10ps
`define CorrCycle {1,1,1,1,0,0,0,0}
`define CorrFrame {`CorrCycle,`CorrCycle,`CorrCycle,`CorrCycle,`CorrCycle}
module RcvAlg(
CntOt,
DtaIn,
Clk,
);
/* Port directions begin here */
output reg [8:0] CntOt;
input DtaIn;
input Clk;
/* Declare needed variables */
reg [39:0] DteRcd;
wire [39:0] corr;
always @ (posedge Clk) begin
DtaRcd = DtaRcd >> 1;
DtaRcd[39] = DtaIn;
corr = DtaRcd ~^ `CorrFrame;
end
endmodule // RcvAlg.v
/*
* This is a testfixture file intended to call a module for
* initial testing.
*/
`timescale 10ns / 10ps // timescale directive
`define SeqZro {0,0,0,0,0,0,0,0}
`define SeqIn {1,1,1,1,0,0,0,0}
`define SgnlSeq {`SeqIn,`SeqIn,`SeqIn,`SeqIn,`SeqIn}
`define Prefix {`SeqZro,`SeqZro,`SeqZro,`SeqZro,`SeqZro}
`define Input {`Prefix,`SgnlSeq,`Prefix}
module testfixture;
wire CntOt; // list the dut variables
reg Clk, DtaIn;
integer count, clock; // list the necessary program variables
RcvAlg dut (.CntOt(CntOt), .DtaIn(DtaIn), .Clk(Clk));
initial begin
$monitor($time,,,"count=%d clock=%d Clk=%b DtaIn=%b DtaRcd=%b corr=%b",
count, clock, Clk, DtaIn, dut.DtaRcd, dut.corr);
begin
count = 0;
clock = 0;
Clk = 0;
DtaIn = 0;
force dut.DtaRcd = 40'h 0;
end
@ (negedge Clk); // wait for a cycle
release dut.DtaRcd;
@ (negedge Clk) DtaIn = 0;
for (index = 0; index < 120; index = index + 1) begin
@ (negedge Clk) DtaIn = `Input[index];
end
end
always begin
#2000 count = count + 1;
if (count == 5) begin
count = 0;
Clk = !Clk;
if (Clk == 1) clock = clock + 1;
end
if (clock == 82) $finish;
end
endmodule // testfixture.v
Attachment:
vlogTST
Description: application/shellscript
/home/designer/Etrema/RcvAlg/RcvAlg.v /home/designer/Etrema/RcvAlg/testfixture.v +libdir-nocase+/usr/Lattice50/UsrLib/lsc +libext+.v