Re: gEDA-user: Icarus Verilog info?

[gene <carzrgr8@xxxxxxxxxxxxx>]

I don't use Icarus Verilog, so I won't/can't comment on your problems  
there.  But I did notice something with your code . . .

  always @ (posedge Clk) begin
    DtaRcd = DtaRcd >> 1;
    DtaRcd[39] = DtaIn;
    corr = DtaRcd ~^ `CorrFrame;
  end

Firstly, you may want to change the "=" to "<=".  The "=" is the blocking  
form and may not be what you desired.  I see that you are creating a shift  
reg with DtaIn as the new data. I don't believe this will build  
correctly.  The correct code would be something like:

  always @ (posedge Clk) begin
    DtaRcd <= DtaRcd >> 1;
    DtaRcd[39] <= DtaIn;
    corr <= DtaRcd ~^ `CorrFrame;
  end

or, more simply:

  always @ (posedge Clk) begin
    DtaRcd <= {DtaIn,DtaRcd[39:1]};
    corr = DtaRcd ~^ `CorrFrame;
  end

BTW, the blocking/non-blocking stuff gets really clarified in this example  
- design a shift reg with and without blocking.  For example:

reg a;
reg b;
reg c;
reg clock;

always @(posedge clock)
 begin
   a = input;
   b = a;
   c = b;
 end

vs.

always @(posedege clock)
 begin
   a <= input;
   b <= a;
   c <= b;
 end

In the first example, at the very first clock edge, a b and c all get set  
to input simultaneuously.  In the second example, it is a shift register.

have fun!
gene


On Sun, 07 Aug 2005 15:50:51 -0400, Harold D. Skank <skank54@xxxxxxxxx>  
wrote:

> People,
>
> I'm using Icarus Verilog as a front end to some Lattice tools.
> Basically I have two questions, an immediate procedural question, then a
> longer term question regarding how to write some ancillary programs.
>
> The procedural question:  I've attached the programs I'm  currently
> attempting to run.  When I call the ./vlogTST program (also attached) I
> get the following output on the control console.  Please ignore the
> syntax error info associated with v:37, I know about that and will
> eventually get it corrected.  What I don't understand is what the v:51:
> message is trying to tell me.
>
> [designer@AMD RcvAlg]$ ./vlogTST
> /home/designer/Etrema/RcvAlg/testfixture.v:37: syntax error
> /home/designer/Etrema/RcvAlg/testfixture.v:37: error: malformed
> statement
> testfixture.v:37: syntax error
> testfixture.v:37: error: malformed statement
> testfixture.v:51: Module testfixture was already declared
> here: /home/designer/Etrema/RcvAlg/testfixture.v:14
>
> For the second question, the old iverilog-fpga man page (apparently
> older than the current iverilog man page) referring to the parch=lpm
> option indicates that users may write interface libraries to connect
> netlists to vendor architecture.  I'm using Lattice devices, and have to
> go through an involved procedure to get from the behavioral code to the
> EDIF model acceptable to my Lattice compiler.  First of all, is this
> possibility (writing the interface library) still available, and if so,
> could you give me some clues about how to start?
>
> Thank you for your consideration.
>
> 	Harold Skank



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