Re: gEDA-user: Renumber in PCB/Was/Is List

[Steve Meier <smeier@xxxxxxxxxxxxxxxxxxx>]

Well.... I am also very interested in pin swapping at the PCB level and
then having the schematic corrected.

Some of the devices use differential I/O it would be nice if these pin
pairs were tied together. But on FPGA's the use of a pair of pins as
differential or single ended is mostly up to the designer.

I have been giving some thought (I need to be careful here because DJ
might be listening and some of you might remember what DJ did with my
meanderings about porn converted to PCB foot prints) to an expanded
hierarchical netlist which would include information about which pins
can be swapped and which of those pins can also be used as differential
pairs. Retaining the order in which the pins are swapped is critical.
Esentialy this is how I manualy do it today.

1) draw schematic
2) generate netlist
3) import netlist into PCB
4) figure out which pins to swap (write them down)
5) edit schematic and swap pins by hand
6) regenerate netlist
7) re-import netlist into pcb
8) repeat steps 4 through 7 until i am more crazzy then usual and the
board is completed.

9) find and fix all the shorted pollygons ;) now i am much more crazzy
then normal


My general idea has been that for pin level swapping the symbol must be
embedded in the schematic. A netlist which tells PCB which pins and
"slots" are swapable. PCB would do its majic, correcting its version of
the netlist and generating a list of swapped pins.. This list of swapped
pins would then be output as a file and a new program would read in the
file and swap the attribute information for the embedded symbols. This
would mean that none of the nets would need to be moved.

Also, I would suggest a move towards XML for these files (new netlist
and swapped pins) 

Steve Meier




On Tue, 2006-08-15 at 15:51 -0400, Patrick Doyle wrote:
> The feature I'm most looking forward to coming out of this exercise is
> the ability to back annotate pin-swap information.  Right now I'm just
> plugging my busses together between the processor and the memory (or
> interface connector, or whatever), anticipating that when I look at
> the rats nest I'll wish I swapped the order of a few things.  If I can
> do that in PCB and then flow the information back to the schematic,
> that will be great.  Otherwise, I'm anticipating a couple of
> iterations of the schematic until I see something I like.
> 
> Perhaps those with more experience in this area in general, and with
> these tools in particular, would care to comment on a better approach.
>  I've got thick skin -- be brutal :-)
> 
> --wpd
> 
> 
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> geda-user@xxxxxxxxxxxxxx
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