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Re: gEDA-user: Hidden rectangle in PCB causing headaches



Hugo,

Thanks for filling in some other cases that the DRC might handle better. In fact, we ran across the last case you describe below on this same design.

Joe

Hugo Elias wrote:

> We've just completed a board which had us scratching our heads when we ran the DRC. We also found problems in the gerber output.


Hi Joe,

I've been having similar nightmares with the DRC. The other
problem is when you have 2 rectangles exactly touching
(with zero gap between them).

I have also thought about a couple of ways the DRC interface could
be improved. As far as I understand it, a DRC error is always between
exactly 2 objects? EG 2 track segments, or a via and a poly. Is
this correct?

So, basically, the user needs to be able to identify exactly which
two objects, even if they are invisible

1. It would be very helpful if the DRC could tell you in the log
which layer(s) the two offending objects were on.

2. instead of colouring in a whole load of things in green, and something in cyan. Why not outline the two objects with a dashed
outline or something. Then the user would immediately be able to see.


3. Instead of saying in the log "copper areas too close".  Why not say
something like "via too close to track" for example.

The other thing that can *really* get you is when a track is accidently
'joined' to a rectangle nearby, even though it doesn't look like it.
I.E. the track is between two other tracks which clear the rectangle,
but the rectangle overlaps the joined track.  This causes PCB to think
there's a short, even though there isn't.

Hugo Elias





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