Re: gEDA-user: Basic questions from a gEDA & Linux noob (replies to Vol15, Issue 24)

[Dan McMahill <dan@xxxxxxxxxxxx>]

John Griessen wrote:
> Dan McMahill wrote:
> I'd think it would be easy
>> enough to create a symbol where the bulk terminal is an implicit 
>> connection like some of the digital chips have already.  Just be sure 
>> that you are sure of the right names.  I'd think this would be 
>> compatible with the existing flow, but perhaps I'm missing something.
> 
> 
> I think its about SPICE netlist depending on pinseq, and pinseq depends on having a pin, or does it?

oh, I see what you're saying.  It seems like that shouldn't be that hard 
to fix, but there's probably something I'm not thinking of.

> Could you make a FET source terminal be a pin with name S and pinseq=3 and somehow have
> a pinseq=4 related to the substrate without having  another pin?  He doesn't want to lose substrate in the netlist,
> just tie it to S for this particular "part" or transistor layout.
> 
> John Griessen

I missed some of the discussion, but surely he wants to tie the 4th 
terminal to global VDD for PMOS and global VSS for NMOS and not have it 
go to the source.  I thought he was doing logic cell schematics?

-Dan




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