gEDA-user: [icarus] task automatic causes assertion

[Günter Dannoritzer <dannoritzer@xxxxxx>]

Hi,

I tried compiling some Verilog code with a 'task automatic' statement 
using Icarus Verilog 0.9.devel s20080429 and got the following assertion:

 >iverilog -o auto2.vvp auto.v
auto.v:16: syntax error
auto.v:3: assert: pform.cc:359: failed assertion lexical_scope == 
pform_cur_module
sh: line 1:  8518 Done                    /usr/lib64/ivl/ivlpp -L 
-F/tmp/ivrlg2784ffa93 -f/tmp/ivrlg784ffa93 -p/tmp/ivrli784ffa93
       8519 Aborted                 | /usr/lib64/ivl/ivl 
-C/tmp/ivrlh784ffa93 -C/usr/lib64/ivl/vvp.conf -- -


When compiling it with the git version I got a segmentation fault:

 >iverilog -o auto.vvp auto.v
auto.v:16: syntax error
sh: line 1:  8470 Done 
/home/hubert/dev//lib/ivl/ivlpp -L -F/tmp/ivrlg21e9b0033 
-f/tmp/ivrlg1e9b0033 -p/tmp/ivrli1e9b0033
       8471 Segmentation fault      | /home/hubert/dev//lib/ivl/ivl 
-C/tmp/ivrlh1e9b0033 -C/home/hubert/dev//lib/ivl/vvp.conf -- -


Is there something I need to change in order for the assertion to work 
when working with the git source?

Below is the Verilog code I used.

Thanks for your help.

Guenter



------------------------------------------------------------------------
module auto;

reg clk;


initial begin
   clk = 1;
   forever begin
     #2.5;
     clk = ~clk;
   end
end

task automatic clk_wait;
   input integer count;
begin
   repeat(count)
     @(negedge clk);
end
endtask

initial begin
   $display("start sim @ %t",$time);
   clk_wait(2);
   $display("end sim @ %t",$time);
   $finish;
end

endmodule




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