Re: gEDA-user: logic analyzers, verilog, and gtkwave...

[DJ Delorie <dj@xxxxxxxxxxx>]

> No, you have to select a bunch of individual signals (they need not
> be the full set of the original bus, or even all related) and then
> "Combine Up" (or Combine Down).

Yup, I figured that out quickly enough.  I just thought automatic
un-expand would be an obvious thing, but it didn't work when I tried
it.  I.e. the fact that it wasn't a toggle was surprising.

What my logic analyzer does... well, download it if you have windows
or wine: http://www.pctestinstruments.com/downloads.htm (it runs in
demo mode if you don't have the hardware).

Anyway... if you have a bus (they call them "groups") and expand it,
it expands like a tree view - it shows the bus line *and* the
component wires under it:

      http://www.delorie.com/pcb/tmp/logicport-bus.png

Here, the "RAMP DATA" bus is expanded into Counter5 through Counter10,
but you can see both the wire signals and the numerical combined value
in the display.


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