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Re: gEDA-user: logic analyzers, verilog, and gtkwave...

DJ -

On Sun, Aug 09, 2009 at 05:51:40AM -0400, DJ Delorie wrote:
> The LA module I wrote is a DDR dual-bank capture, [chop]
> A perl script turns them into a VCD file that gtkwave can read :-)

Awesome.  I hope you'll write this up more, and publish code.
 
> Question: Can gtkwave be told to break up a bus into its component
> signals?

It's in the Edit menu, called "Expand" (F3).

   - Larry


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