gEDA-user: Layer selective DRC

[Kai-Martin Knaak <knaak@xxxxxxxxxxxxxxxxxxx>]

Hi. 
My current project calls for big currents and and fine pitch SMD components, 
too. So I opted for four layers with 35 Âm copper on outer and 105 Âm copper 
on inner layers. Now, my fab requests 250 Âm clearace on layers with extra
copper. To comply with this, it would be handy to have different sets of design
rules fpor differnt layers. 

In the absence of that feature, is there any way to restrict a DRC check just to
one specific layer?

---<)kaimartin(>---
-- 
Kai-Martin Knaak                                  tel: +49-511-762-2895
UniversitÃt Hannover, Inst. fÃr Quantenoptik      fax: +49-511-762-2211	
Welfengarten 1, 30167 Hannover           http://www.iqo.uni-hannover.de
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