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Re: gEDA-user: How to do PCB Autorouting with non-plated holes

Thanks for all the suggestions. I've played with it a bit and come up with an example for a 200mil radial capacitor below: 

Element["" "" "C0" "" 97000 208000 8000 -28000 0 100 ""]
(
        Pin[0 0 0 3000 6600 3000 "" "1" "hole,square"]
        Pin[20000 0 0 3000 6600 3000 "" "2" "hole"]
        Pad[0 0 100 0 6000 3000 9000 "" "1" "onsolder,square"]
        Pad[20000 0 20100 0 6000 3000 9000 "" "2" "onsolder,edge2"]
        ElementArc [10000 0 20000 20000 0 360 1000]

        )
I have never had to muck with footprints manually, so it's a bit of a learning curve for me. The footprint Colin provided doesn't have a solder mask that's quite right (Resistor_TH_FarPads.fp). It appears that in order to fix is, I had to add the "square" flag to the Pin as well as to the Pad. 

-Cory

On Tue, 23 Aug 2011, Kai-Martin Knaak wrote:


Cory Papenfuss wrote:


I thought about that... making different footprints that don't
have copper on the component side of the pins.  Since that would require
making new footprints for pretty much everything,


Well, you could do the heavy lifting with an awk script:

If the current line is a pin,
   set the diameter of the pin to zero and add a hole flag
   ouput a round pad with the diameter of the pins annular ring
else,
   output the current line unchanged.



I was hoping for a
different solution... :)  It seems like it would be a relatively common
thing for hobbyists to want (whether it's a milled or home-etched board),
so I thought there might be a setting on the autorouter config to "ignore
component hold plating" or something.


IMHO, the copperless pin solution is superior. It models the layout like
it is in reality.

That said, both autorouters have a problem with user level configuration,
or rather the lack thereof. Features that would make auto routing a much
more viable option than it is now:


* alternatively minimize via count, or minimize overall track length

* options to not autoroute particular nets/pins/components

* track parameters that depend on the net it connects

* preferred routing direction of a layer

* Non-copper avoid-areas with different levels of importance.
 (prefer-to-avoid --> avoid at all cost)

---<)kaimartin(>---
--
Kai-Martin Knaak
Email: kmk@xxxxxxxxxxxxxxx
http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53
increasingly unhappy with moderation of geda-user



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*************************************************************************
* Cory Papenfuss, Ph.D. Electrical Engineering, PPSEL-IA                *
* Research Associate, Vibrations and Acoustics Laboratory               *
* Mechanical Engineering                                                *
* Virginia Polytechnic Institute and State University                   *
*************************************************************************



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