[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]

Re: gEDA-user: How to do PCB Autorouting with non-plated holes



I thought about that... making different footprints that don't have copper on the component side of the pins. Since that would require making new footprints for pretty much everything, I was hoping for a different solution... :) It seems like it would be a relatively common thing for hobbyists to want (whether it's a milled or home-etched board), so I thought there might be a setting on the autorouter config to "ignore component hold plating" or something.

Thanks!
-Cory

On Tue, 23 Aug 2011, Colin D Bennett wrote:

On Tue, 23 Aug 2011 07:15:54 -0400 (EDT)
Cory Papenfuss <papenfuss@xxxxxxxxxxxxxxxx> wrote:

 	Hey, all.  I've used PCB on an off for 10 years and recently
have been getting familiar again with the rest of gEDA which has
become a great set of tools!

 	Anyway, I've been using a board mill to make 1 and 2-layer
prototypes of typically through-hole components.  The trouble is when
the autorouter chooses to use a component pin as a via to transition
to the other layer.  If it's a part that doesn't have room to solder
the topside (most parts... DIPs, ribbon-cable connectors,
can-electrolytic caps, etc), it's very difficult to connect both
sides.

 	I typically check manually, but it's tedious and I often
miss some.  Is there any way to set up the autorouter to ignore
component-layer pads, but still route on the component layer
elsewhere?  I've scoured the web for ideas but come up only with
kludging a "no-autoroute-zone" by placing copper on the component
layer before autorouting.

Since you have no plated holes, the component footprints are really
incorrect.  Through-hole footprints generally specify plated holes for
all pins.  However, I think this does not need to be the case.  I've
had similar problems with manual routing, when I accidentally route
traces to through-hole pins on non-plated-through-hole boards which
necessarily be soldered on that side.

Here is an idea of how you could use a footprint that specifies that a
copper annulus exists on the far side of the board only.  Instead of a
plated pin, it includes a pure hole and an SMT pad on the far side.
You can test it and see if it does what you want.  You could also put a
pad on the component side too, if you were going to solder the leads
there as well, and thus create a via with the component lead.

See attached footprint file.

Regards,
Colin



*************************************************************************
* Cory Papenfuss, Ph.D. Electrical Engineering, PPSEL-IA                *
* Research Associate, Vibrations and Acoustics Laboratory               *
* Mechanical Engineering                                                *
* Virginia Polytechnic Institute and State University                   *
*************************************************************************



_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user