Re: gEDA-user: gschem vs. PCB diode pin numbering

[Colin D Bennett <colin@xxxxxxxxxxx>]

On Thu, 25 Aug 2011 22:41:28 +0200
Levente Kovacs <leventelist@xxxxxxxxx> wrote:

> On Thu, 25 Aug 2011 14:03:35 +0200
> Kai-Martin Knaak <knaak@xxxxxxxxxxxxxxxxxxx> wrote:
> 
> > Why not?
> 
> Pinnumbers are "numbers" in the first place. Former versions of
> netlisters/PCB got confused by non-digital pinnumbers.

Who cares?  There's no reason to restrict ourselves from doing it right
when the tools support it now.

> With this approach you have to have a SOT23 footprint with 1,2,3
> pinout, A,K,NC pinout, A1,A2,K pinout, B,C,E pinout etc. Sooner or
> later, your library will contain duplicated data. What if you
> discover that you want to modify the shape of the SOT23.fp footprint?
> You have to modify all of them. Yuk.

I won't get into it too much here; the logical vs. physical pinnumber
assignment has been discussed in much detail before.
<http://thread.gmane.org/gmane.comp.cad.geda.user/32149/focus=37188>

> I think a footprint must have only *one* pinout, that is a standard
> pinout of the package. Have an intermediate layer (scripts, database,
> pinmaps, etc.) that do the heavy lifting for you.

Maybe in an ideal world (when pin mapping orthogonal to the schematic
and layout is introduced), but for now, the only two ways to handle
transistors etc. properly is to either

(1) create separate symbols for each pinout, where pinnumber is
assigned numerically according to package pin number (1, 2, 3).
For instance, you would need symbols NPN-EBC, NPN-BCE, etc., and
potentially different symbols for packages with a fourth âtabâ pin such
as SOT-223-4 <http://www.onsemi.com/pub/Collateral/NSS40300MZ4.PDF>; or

(2) create separate footprints for each pinout, using logical
pinnumbers B, C, E, and footprints that assign these to appropriate
package pins; then you only need two BJT symbols âNPN.symâ and
âPNP.symâ that use these logical pins; this supports packages with a
fourth âtabâ pin without cluttering the schematic, and allows such
details as pinout to be deferred until after basic schematic drawing.

Do you really want to delete and re-add each of your dozens of
transistors in gschem when you change the transistor to one with a
different pinout?  If you use a logically-pinned symbol, you can easily
change the pinout by just editing the footprint attributes (gattrib,
gschem property editor, export/import to/from spreadsheet, etc.).

Conversation regarding TO-92 transistor package pinouts:
<http://thread.gmane.org/gmane.comp.cad.geda.user/37190/focus=37197>

Well, I always say I won't get into the logical/physical pinning
debate, but I always do. :-)  For me, using logical pins on the
schematic symbols such as transistors and diodes (*especially* diodes in
IC packages like SOT-23) is the only way that makes sense ... at least
until proper pin mapping is implemented.

Regards,
Colin


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