On Wed, 2011-08-31 at 20:41 -0400, DJ Delorie wrote:
> The original bug for my layer visibility patch, IIRC, is a groups line
> like "c,1;s,2" - note that the c/s are listed before the 1/2. The
> "max_layer+1" trick is used for both the c/s magic layers *and* the
> silk layers.
Come to think of it, it might have been that which caused the issue with
PCB+GL - I wonder if the test I was hitting should only have let it
check visibility within the group for copper layers, not "silk _or_
copper".
The "hacked up very quickly" fix I made in the PCB+GL branch was:
commit f059e9536659aedefa4a91c249a40b8eafe309d4
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Date: Tue Aug 30 20:48:13 2011 +0100
Fix layer on/off rendering
I'm not certain this is correct at all. It works around failure
to switch layer visibility on / off after
commit 9768e060fad7bc3dfc366da76ea1db8154005018
"Fix layer visibility logic for some boards."
After which, copper layers on the component / solder group
would still be drawn unless the silk layer was also turned off.
This appears to be due to the GL HID's custom drawing routines
not checking the return of the (HID)->set_layer function in certain
instances.
This fix is almost certainly WRONG.
diff --git a/src/hid/gtk/gtkhid-gl.c b/src/hid/gtk/gtkhid-gl.c
index 751ddef..509815b 100644
--- a/src/hid/gtk/gtkhid-gl.c
+++ b/src/hid/gtk/gtkhid-gl.c
@@ -1566,7 +1566,7 @@ GhidDrawLayerGroup (int group, const BoxType * screen)
strcmp (Layer->Name, "route") == 0)
rv = 0;
- if (layernum < max_copper_layer /*&& Layer->On*/) {
+ if (layernum < max_copper_layer && Layer->On) {
if (!first_run)
From looking at the code again, and your comments - I suspect the line:
+ if (ni >= 0 && ni < max_layer + 2
+ && PCB->Data->Layer[ni].On)
+ break;
should perhaps read:
+ if (ni >= 0 && ni < max_layer
+ && PCB->Data->Layer[ni].On)
+ break;
(So that it doesn't early-exit and assume the group is visible because
it happened to find the silk-layer turned on).
It would also need the test after the for-loop modifying to reject a
visible silk layer if the test fell of the end of the for-loop having
not found a visible copper layer (instead, only silk).
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)
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