Stephen Williams wrote: > Can someone who has access to any of the Big-3 Verilog simulators > try to run the attached example for me? I'm trying to work out some > SDF semantics and I've seen some SDF files that have constructions > that are demonstrated by this example. I found a bug in the SDF file that I posted originally, so I've attached a fresh zip file with the verilog source and sdf file. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."
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