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Re: gEDA-user: PCB not liking my refdes



On Wed, Dec 3, 2008 at 8:33 PM, Ethan Swint <eswint.ramu@xxxxxxxxxxx> wrote:
>
>>> PCB doesn't like refdes's that end in lower case letters.  It's
>>> documented, too - used for manual slotting.
>>>
> I looked in the PCB manual (http://pcb.sourceforge.net/pcb-cvs/pcb.html)
> and the PCB FAQ (http://pcb.sourceforge.net/faq.html), but I found no
> reference to slotting or the trailing lower case letter being reserved.
> I was, in hindsight, able to find discussions on the mailing list of
> this behavior with a search for "PCB "lower case letter" ".  Is there
> another PCB reference document which I should be consulting, or is this
> something that should be added to the PCB manual?
>

See section 7.5 Netlist File Format

Netlists read by Pcb must have this simple text form:

     netname [style] NAME-PINNUM NAME2-PINNUM2 NAME3-PINNUM3 ... [\]


for each net on the layout.
where "netname" is the name of the net which must be unique for each
net, [style] is an optional route-style name, NAME is the layout-name
name given to an element, and PINNUM is the (usually numeric) pin
number of the element that connects to the net (for details on pin
numbering see Element Objects). Spaces or tabs separate the fields. If
the line ends with a "\" the net continues on the next line and the
"\" is treated exactly as if it were a space. If a NAME ends with a
lower-case letter, all lower-case letters are stripped from the end of
the NAME to determine the matching layout-name name. For example:

          Data U1-3 U2abc-4 FLOP1a-7 Uabc3-A9

specifies that the net called "Data" should have pin 3 of U1 connected
to pin 4 of U2, to pin 7 of FLOP1 and to pin A9 of Uabc3. Note that
element name and pin number strings are case-sensitive. It is up to
you to name the elements so that their layout-name names agrees with
the netlist.


(* jcl *)

-- 
http://www.luciani.org


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