Re: gEDA-user: Missing trace

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Mon, 2008-08-25 at 21:54 -0400, Ian Chapman wrote:
> I have almost finished debugging the mostly SMT part of my new board.
> (I'll send DJ a photograph once fully assembled).  It's going much
> better than I thought it would.  I have three annoyances due to  missing
> three traces.  Backtracking to the schematic they are signals between
> sheets.  I used the add/components/I/O generic/input_1.sym type of off
> page connection.  The net attribute is the same at both ends sig:1 etc.
> I have many inter-page signals that are correctly linking my 14 sheets
> so I must have that right.  I did have a history of deleting connections
> to correct DRC errors but o optimize rats always showed the missing
> connections.  Right now o tells me all is okay.  I guess I skipped a
> step, any pointers would be welcome.  Regards Ian.

I realise this is an old thread, but I came across a bug report in the
bug tracker recently.. it is apparently a gnetlist bug that connections
are dropped if they just have off-page IO connections on them, and
nothing else.

As a workaround, try placing a dummy component on the net - which has no
footprint. The bug reporter said this is what they did, choosing a
component name which was then possible to search for and remove in the
resulting netlist. Pain, I know - but not as bad as missing connections.

We'll try to get this fixed for the 1.6.0 release.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)



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