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Re: gEDA-user: overlapping via changes



Kai-Martin Knaak wrote:
2. Vias which violate this rule in a *.pcb file are preserved at load
   time.

Thus, PCB will make a modest attempt at preventing users from making
vias that might be difficult to manufacture, but if the user finds a
way around the restriction, PCB will let them get away with it.
Simply moving an existing via is an adequate way around it.

Thanks. I'll put this to the wiki.
Back then when I used protel we actually had cases where overlapping
were holes deliberate. The hole had to be non-round and clad with metal. So regular milling wouldn't do.
Can you give a reason? - I can only imagine a mechanical one.
When you put it on the Wiki, pleas also explain, that doing this is electrical and thermal nonsens, because the circumference of a hole is proportional to the diameter and 2 holes confined in a given length along the direction connecting the centers have maximum surface, if they are either identically 1 big hole or 2 holes that exactly touch each other. For the partial overlap, the normalized circumference u is given by:

U/L = u = 2r * (pi - acos(1/2r - 1))

where r = R/L, L is the diameter of the overlapping holes and R is the drill-bit radius. This function is valid between r = 0.25 where the holes just touch and r = 0.5 where the holes melt to one big circular with R = L/2. It has a minimum at ca. 0.295

Hopefully I didn't foul the math, check it ;-)


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