Re: gEDA-user: Verilog 2001

[Stephen Williams <steve@icarus.com>]

matt@ettus.com said:
> What is the state of, and planeed future for Verilog 2001 constructs
> in  Icarus? I'm specifically interested in bit selects in arrays,
> arrays of instances, multi-dimensional arrays, and generate constructs.

Some of Verilog-2001 is already supported, including signed arithmetic,
declaration assignments, port declaration lists, and other items I forget.

Arrays of primitive gates (i.e. bufif drv [31:0]) already work fine.
Arrays of modules are harder, but someday I'll get to them. Generate
statements would not be far behind module instance arrays, but they
are not on my to-do list for 0.8. I agree that working generate
syntax would be extremely kool, and is not as hard as it looks.

I'm also keeping an eye on SystemVerilog developments, and will be
bringing in some bits soon. Integral types in particular are next on
my to-do list.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
steve at picturel.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."