Hello Matt and Stephen! Am Donnerstag, 13.02.03 um 01:48 Uhr schrieb Stephen Williams:
Some of Verilog-2001 is already supported, including signed arithmetic,
declaration assignments, port declaration lists, and other items I forget.
Nice deja vu.Arrays of primitive gates (i.e. bufif drv [31:0]) already work fine. Arrays of modules are harder, but someday I'll get to them. Generate statements would not be far behind module instance arrays, but they are not on my to-do list for 0.8. I agree that working generate syntax would be extremely kool, and is not as hard as it looks. I'm also keeping an eye on SystemVerilog developments, and will be bringing in some bits soon. Integral types in particular are next on my to-do list.