Re: gEDA-user: putting it all together

[cfk <cfk@pacbell.net>]

Dear John:
    Let me tighten it a bit. I am striving to understand the front-end and
back-end design flow for a CMOS chip. I have in mind a particular design
that I am currently prototyping in an FPGA. The design is expressed in
Verilog. Basically, its a wireless networking chip. My current hope is to
understand how to get from Verilog to a layed out CMOS IC. The process is
less important that the understanding of how it all works. Since I cannot
obtain Cadence or Mentor tools without decimating my savings account,
mortaging my wife and other uninteresting activities, I am trying to
understand how Icarus Verilog may synthesize a netlist, then feed that into
Magic (hopefully), place and route the cells in accordance with the netlist,
understand enough of the use of IRSIM & Spice to see that what I have
created makes some sort of sense and then admire a GDS file or two. I dont
intend to take this idea to masks, this is an attempt to understand how it
all fits together.

Does that help a bit on focusing?


----- Original Message -----
From: "John Sheahan" <jrsheahan@optushome.com.au>
To: <geda-user@seul.org>
Sent: Saturday, February 22, 2003 2:12 PM
Subject: Re: gEDA-user: putting it all together


> On Sat, Feb 22, 2003 at 11:05:44AM -0800, cfk wrote:
> > Gentlemen:
> >     I've spent a few months trying to get my hands around
> > undestanding the design flow sufficient to understand how to get an IC
> > designed.
>
> Charles
> which part of the spectrum of IC's are you interested in?
>
> there is a long way to go before PD tools would be considered for
> a current generation digital process.
>
> Your question is a little broad at this point.
> John