Re: gEDA-user: putting it all together

[John Sheahan <jrsheahan@optushome.com.au>]

On Sat, Feb 22, 2003 at 02:20:10PM -0800, cfk wrote:
> Dear John:
>     Let me tighten it a bit. I am striving to understand the front-end and
> back-end design flow for a CMOS chip. I have in mind a particular design
> that I am currently prototyping in an FPGA. The design is expressed in
> Verilog. Basically, its a wireless networking chip. My current hope is to
> understand how to get from Verilog to a layed out CMOS IC. The process is
> less important that the understanding of how it all works. Since I cannot
> obtain Cadence or Mentor tools without decimating my savings account,
> mortaging my wife and other uninteresting activities, I am trying to

Hi Charles

selling the family into slavery is probably insufficient now anyway.
There are some points you seem to have missed. 

let me perhaps start something by listing a 'typical' flow.

1  idea
2  specification
3  bahavioural test benches + behavioural model   <= larger chips.
4  RTL coding, module test benches, simulation
4a get models of memories, cores, gates etc
5. trial module synthesis and rough check timing + size
6. module integration (higher level structure), chip test benches
7. chip level RTL simulation
8  test bench coverage analysis
9  power estimation
10 IO insertion
11 package bonding
12 floorplanning and wireload model generation
13 timing driven chip synthesis
14 rough chech chip level timing (STA)
15 formal verification (check synthesis)
16 test insertion (full scan? logic bist? jtag, memory bist?)
17 timing driven place and route, with local resynthesis
18 power routing and verification of power integrity
19 parametric extraction, timing backannotation
20 STA
21 gate level full timing sim (maybe)
22 spice on critical paths with full parametric backanno (just maybe)
23 test vector preparation 
24 schematic extraction from layout database and compare to gate netlist
25 more FV (gate-gate) verifying layout tools
26 metal utilization, antenna effect , crosstalk analysis etc chacks
   on layout database 
27 DRC of layout database
28 GDSII generation
29 make masks
30 fab
31 wafer probe
32 package protos
33 verify test program, all DC, AC, functional tests
34 verify prototypes in system

I'm sure I have forgotten a few too.  I suspect only 3-8 have some level of
open sourced coverage today. 

john