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Re: gEDA-user: DRC: "Element Z50 has 5 silk lines which are too thin"

David Kuehling wrote: 
Hi,

just another strange DRC error.

This is caused by the oldlib-generated footprint "SMT_DIODE 15 8":

  Rules are minspace 5.92, minoverlap 5.91 minwidth 5.91, minsilk 7.09
  min drill 1.00, min annular ring 15.75
  Element Z50 has 5 silk lines which are too thin
  near location (1942.91,1350.39)
  Found 1 design rule error

I thought PCB would just increase too thin silk lines when exporting
gerber files.  At least it does so for fonts...

It does not and I would object to it increasing too thin silk lines automatically. Perhaps doing that causes silk on a pad for example.

My take is silk lines that are too narrow are real DRC violations.

-Dan



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