Re: gEDA-user: pcb insulator layer

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Tue, 2008-02-05 at 20:27 -0500, DJ Delorie wrote:
> The solution is to realize that pcb is open source.
> 
> Change it to not export vias on those layers.
> 
> > When exploring different exports with gerbv ad gv I noticed the
> > postscript differed.  a polygon on layer 6 named outline also was
> > output on layer 5 with the original polygons in postscript, but in
> > gerber output that polygon was only on 6 (as it is defined in pcb)
> 
> Intentional.  Fabs using gerber don't need to know the outline on the
> copper plots, but it's really handy to have on the postscript prints.

That is really black magic. How long has it done that? I've never
noticed!

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)



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