gEDA-user: Users of verilog and VHDL gnetlist backends -=(BREAKAGE IN 1.4.0)=-

[Peter Clifton <pcjc2@xxxxxxxxx>]

WARNING, USERS OF VHDL and VERILOG NETLIST BACKENDS, DON'T UPGRADE TO 1.4.0

Hi all,

I was doing some work looking at adding attribute output to the verilog
backend, and discovered some breakage. (It is dead in 1.4.0).

I've done some tests, and it seems that the VHDL backend is also
affected.

This was an unfortunate side-effect of code changes introduced for
slotting with spice-sdb between 1.3.0 and 1.4.0.

I'm working on fixes to the appropriate .scm files, but until those are
ready (and will go in 1.4.1), I'd suggest that anyone needing those
back-ends does not upgrade past 1.3.0.

Anyone interested, I have a gnet-verilog.scm backend fixed, and also
handling attribute output for modules. (Useful for simulation, esp. when
gnucap's Verilog-A support is out!)


Sorry for the breakage, it slipped past the gnetlist test suite when I
made the changes for spice-sdb. I hope to increase the gnetlist
test-suite coverage as a result of this problem. It turns out that only
a handful of the backends were being tested by it at all.


Regards,

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)



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