Re: gEDA-user: my first Verilog project

["Udi Finkelstein" <geda@xxxxxxxx>]

On Feb 9, 2008 3:14 AM, DJ Delorie <dj@xxxxxxxxxxx> wrote:

>
>
> > Was the need for the 2$ part due to pins or due to resources?
>
> Resources.  There weren't enough intermediate nodes to do all the
> logic equations, I ran out of "product terms".  The minimal design in
> a '72 used about 60% of the resources, a little more than half (which
> would have fit in the '36).  Once I realized that I needed the '72
> anyway, I added some features to use up the remaining pins and
> resources - blanking, polarity, LZ, latch.
>
>
I'm not an expert on Xilinx's CPLDs and the Xilinx synthesis tools,
but there are a few things that might have improved the utilization of
your code:

You wrote in the 'sevenseg012' module:

always @ (ibcd)
begin
 case (ibcd) // abcdefg
 0 : oseg = 7'b1111110;
 1 : oseg = 7'b0110000;
 2 : oseg = 7'b1101101;
 default : oseg = 0;
 endcase
end

Using
default : oseg = 7'bx;

Will let the synthesizer optimize the logic with don't cares for all
the non-used combinations.
The same applies to the 'sevenseg' module.

There are also a few style issues. I don't know if the Xilinx tools
support the Verilog 2001 syntax, but if it does, you can use "always
@(*)" for any combinatorial block, which will generate the sensitivity
list automatically.

Verilog 2001 also allows you to write:

module sevenseg(
    input [3:0] ibcd,
    output reg [6:0] oseg,
);

which is more in ANSI-C style than:

module sevenseg(ibcd, oseg);
    input [3:0] ibcd;
    output [6:0] oseg;

    reg [6:0] oseg;

Also module 'bcd' could simply be written as:

always @ (ibin)
begin
  bcd2 = (ibin/100) % 10;
  bcd1 = (ibin/10) % 10;
  bcd0 = ibin % 10;
end

instead of separate 256 case entries.
Any decent synthesizer would synthesize the above equally or even
better than 256 discrete case entries.

Also note the use of blocking assignments (=), not non-blocking
assignments (<=). It is recommended to use blocking assignments for
combinatorial blocks and non-blocking assignments for sequential
(clocked) blocks.

Udi


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