Re: gEDA-user: my first Verilog project

[DJ Delorie <dj@xxxxxxxxxxx>]

>  default : oseg = 0;
>  endcase
> end
> 
> Using
> default : oseg = 7'bx;
> 
> Will let the synthesizer optimize the logic with don't cares for all
> the non-used combinations.

I needed the zero state to do blanking at one point, but I'll try the
X version and see what happens.

> There are also a few style issues. I don't know if the Xilinx tools
> support the Verilog 2001 syntax, but if it does, you can use "always
> @(*)" for any combinatorial block, which will generate the sensitivity
> list automatically.

It might.  I just googled for "verilog tutorial" and went with that.

> Also note the use of blocking assignments (=), not non-blocking
> assignments (<=). It is recommended to use blocking assignments for
> combinatorial blocks and non-blocking assignments for sequential
> (clocked) blocks.

I tried both, but the way I sequenced the statements, it didn't make a
difference.


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