Re: gEDA-user: gnetlist verilog back end gnet-verilog.scm

[Paul Tan <pt75234@xxxxxxx>]

Hi John,

There is a BASH script "geda_hier_tools.bsh" to generate
Hierarchical Verilog netlist with example that I posted last
month:

http://archives.seul.org/geda/user/Jan-2009/msg00056.html

Note that you need to have your gnetlistrc in each of those
Verilog project to contain:

(hierarchy-traversal  "disabled")

This is needed, because Verilog needs a "non-flatten"
hierarchy. The example shows that.

Hope that helps

Best Regards,
Paul Tan



-----Original Message-----
From: John Griessen <john@xxxxxxxxxxxxxx>
To: gEDA user mailing list <geda-user@xxxxxxxxxxxxxx>
Sent: Mon, 9 Feb 2009 1:22 pm
Subject: gEDA-user: gnetlist verilog back end gnet-verilog.scm



This is probably a Mike Jarabek question:

I don't get usable hierarchic netlist output when I have placed 
schematics and
use the gnet-verilog.scm back-end.
It drops the module definitions and endmodule statements of the placed 
symbols
that refer to schematics.

So, is that the normal behavior, and I need to not use hierarchy, and 
run
gnetlist on every schematic, then cat them together?

There seems to be no existing gnetlist concatenate function.  Would 
handling
this in scheme be difficult?

By "this" I mean taking all the files referred to by source= attribs 
and running
gnet-verilog.scm on each in order,
then putting that to the gnetlist output.   gnet-verilog.scm is ready 
to create
a one level netlist -- one module's worth of
verilog.

Using a makefile is the obvious thought.  Make could just take a list 
or all
..sch in a dir and run them and cat them together
to a filename.

Handling it without make complexity separate from the back end chosen 
would be
nice
though, so I ask, "Anyone seen existing scheme code that could use
source=verilog_io.sch to trigger running it again on the
referenced file then outputting that to the same place as usual?

Thanks,

John Griessen
--
Ecosensory   Austin TX


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