Re: gEDA-user: Interesting board defect

[Ben Jackson <ben@xxxxxxx>]

On Sat, Feb 14, 2009 at 06:09:36PM -0500, DJ Delorie wrote:
> 
> Yeah, it looks like you violated the "minimum trace width" on the
> hairline copper traces between the two pads, and they broke off and
> got glued down by the solder mask.

Yep.  If you have an unpopulated board and a stout bench supply I'd try
hooking it up and ramping the current limit to try to burn those traces
off.  I've even managed that on boards where there were already
components and I could pump enough amps at the target VCC.

> I don't think it's something our DRC detects.

It's not really a DRC problem.  The polygon clearance code should
eliminate slivers when they form.  I've thought about how to do it, but
I don't have any ideas that would work well in our dynamic add/remove
setup.  It would be pretty easy to do as a post-processing step.

-- 
Ben Jackson AD7GD
<ben@xxxxxxx>
http://www.ben.com/


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