Re: gEDA-user: transition of pcb internal units to metric (SI, mm)

[David Smith <Dave.Smith@xxxxxx>]

Andrew Miner wrote:
> The current standard for wafer diameter is 300 mm (11.8") => 109 sq inches.
> You would loose about 1/4 of the area to the edge effects on the wafer so
> you are looking at ~75 in sq of usable space.  When you consider that most
> of the parts that we use on our PCBs have an IC die size of (much) less than
> 1/2 of a sq inch, you could reasonably hope to fit 100 different chips on a
> wafer.  That would drop the $1 to $3 million dollars down to $10,000 to
> $30,000 per chip on the wafer.  They can then make a hundred wafers easily
> on the first batch, so there would be 100 of each chip for that cost.   If
> you were talking about a 0.1 sq inch chip, as a student project, you might
> be able to get in cheaper than that.

I am not an expert on ASIC manufacture, but I think that you've made
some incorrect assumptions there.

Yes, the standard wafer at current cutting-edge processes is 300 mm
(although for older and non-standard processes, smaller wafers are
common); however, I don't believe that you'd be able to get a mask
(a.k.a. "reticle") set that would cover the entire surface of that
wafer.  A reticle will only cover a proportion of the wafer's surface,
and to cover the whole wafer surface, the reticle will be used to expose
the surface of the wafer repeatedly, using a piece of equipment called a
"stepper".

Therefore, the maximum number of different chips you can have on a wafer
is limited by the maximum reticle size, not the wafer size.

At a guess, I'd say that the maximum image size would be about 100 mm x
100 mm (once exposed on the wafer surface).  Also, the larger the
reticle, the more uneven the spread of devices (e.g. one device in the
MPW may get 4 working impressions, but another may get two because it's
hanging over the edge of the wafer in the other two instances).

This would, however, still give you one hundred 100mm^2 different
devices within a single reticle, and 100mm^2 is still a lot of
transistors at 90 nm or 65 nm.

Of course, you could in theory make multiple mask sets to image
different parts of the wafer, but that would defeat the object of the MPW.

You would also have to take into account that you're unlikely to get all
the MPW's customers to agree to a uniform die size, so some of the dice
will be lost as the wafer is cut up, since the saws used will typically
only make straight cuts all the way across the surface of the wafer -
you can't turn corners.  So, out of the 100-wafer lot, maybe 25 of them
will be cut for your die.


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