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Re: gEDA-user: transition of pcb internal units to metric (SI, mm)

   > From: David Smith <[1]Dave.Smith@xxxxxx>
   > Date: Tue, 8 Feb 2011 14:32:24 +0000
   > I am not an expert on ASIC manufacture, but I think that you've made
   > some incorrect assumptions there.
   > Yes, the standard wafer at current cutting-edge processes is 300 mm
   > (although for older and non-standard processes, smaller wafers are
   > common); however, I don't believe that you'd be able to get a mask
   > (a.k.a. "reticle") set that would cover the entire surface of that
   > wafer.  A reticle will only cover a proportion of the wafer's
   surface,
   > and to cover the whole wafer surface, the reticle will be used to
   expose
   > the surface of the wafer repeatedly, using a piece of equipment
   called a
   > "stepper".
   Okay, I was not fully awake this morning, so I did make some mistakes.
   Yes the 300 mm wafers use steppers, and that is how they can get down
   to the 65 nm and finer resolutions.  In that case you would have a
   small portion of the die image.  I was still half asleep and thinking
   along the um scale technology we have at my (former) university with a
   4" wafer line that uses a full 4" mask.   There were some masks there
   that had many unique designs over the whole 4" mask (not just step and
   repeat), and we were able to fab those on wafers in house.
   One of the companies that currently offers this service is MOSIS
   [2]http://www.mosis.com/about/whatis.html  and as I remember they did
   offer great prices for students as this albeit old pdf shows:
   [3]http://users.ece.gatech.edu/rincon-mora/research/mosis_submsn.pdf
   You would need to quote out current prices, but a student use to get a
   custom ASIC for as little as $3250.  Commercial prices would be higher
   especially as you  approach 90 nm or finer.
   Andy Miner

References

   1. mailto:Dave.Smith@xxxxxx
   2. http://www.mosis.com/about/whatis.html
   3. http://users.ece.gatech.edu/rincon-mora/research/mosis_submsn.pdf


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