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Re: gEDA-user: Icarus Verilog: selecting parts of an array

Stephen Williams wrote:


integer i;
for (i = 0; i < 64; i = i + 8) begin
   @posedge(clk);
   data = test[i:(i+8)];
end

Don't you mean @(posedge clk)?
Yep. I just typeed it of the top of my head as I didn't have the source code handy at the time. My Verilog is rusty but I'm back on to a new project which should quickly refresh my memory ;-)

Is the above a valid Verilog code snippet (ignoring the erroneous posedge statement) ???

Thanks,
Brendan Simon.