Re: gEDA-user: Icarus Verilog: selecting parts of an array

[Stephen Williams <steve@icarus.com>]

integer i;
for (i = 0; i < 64; i = i + 8) begin
    @posedge(clk)
    data = test[i:(i+8)];
end

Don't you mean @(posedge clk)?

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
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