gEDA-user: Icarus Verilog: selecting parts of an array

[Brendan J Simon <brendan.simon@bigpond.com>]

I get a compile error if I try the following in a test harness.  Is it 
an Icarus bug or a Verilog limitation ???

integer i;
for (i = 0; i < 64; i = i + 8) begin
   @posedge(clk)
   data = test[i:(i+8)];
end

Also, is there such things as local variables in Verilog ???
The above example is within a task which may support local variables.

I'm subscribed to one of the geda lists but I'm not sure which one (user 
or dev).  Could any replies be CC'd to my email.

Cheers,
Brendan Simon.