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Re: gEDA-user: Vias with zero clearance in PCB?



Friends -

On Mon, Jan 09, 2006 at 09:14:35PM -0500, DJ Delorie wrote:
> 
> > I'd like to place numerous vias in a cluster to assist with heat
> > transfer or RF shielding integrity. How can I do this in PCB?
> 
> [chop] the only way to do > so is to add a second polygon in that
> area that does not have the "clear pins/vias" flag set.

Cute trick.  Thanks!

> There is currently no way to specify this on a per-via basis.

I have hacked my way to this result by adding a thick trace
(thicker than the clearance size of the via) that is marked
with a "j" to join the polygon.

    - Larry

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