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Re: gEDA-user: Vias with zero clearance in PCB?



Larry Doolittle wrote:

I have hacked my way to this result by adding a thick trace

(thicker than the clearance size of the via) that is marked
with a "j" to join the polygon.



My favorite method is to use a single zero-length line to make a circle that perfectly fills the clearance.
Of course, the line has the join property set. This way you can put them in tight
spaces. You can also use four arcs with the join property to make a "ring" that fills the clearance.
(you can even leave out one of the arcs for ultra-tight spaces). Once you
construct one via with its zero-length line or 4 arcs, I like to copy it into a buffer, then the paste tool
effectively becomes a zero-clearance thermal tool. Note that you can paste right
on top of existing vias because pcb will prevent the via stacking.


The major down-side to this technique is that if you adjust the via clearance you
also need to adjust the thickness of the "solid thermal".


Here is how to construct a zero-length line: Use the line tool to draw a single short line (start with
your desired thickness or not). Now use the arrow tool to move one of the line end points on top
of the other. Viola' a zero-legnth line (it's just a circle of copper).


Tip: you can use the move-to-current layer (m) key to change the connection to a different layer.
Tip: you've got multiple buffers, use them. Keep one of these solid filed vias handy in paste buffer 5.
Tip: you can save one of these solid-plane vias as an element (don't convert it to an element, element
files can include lines, and vias etc. This allows a break-out pattern to be saved along with a BGA
footprint for instance). That way you can have it available as a library element.
Tip: make a bunch of these of different sizes (and different layers if you're so inclined) and save them
in your library.


harry