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Re: gEDA-user: Test pads in PCB

Stuart Brorson wrote:
So my question: Has anybody here tried placing test pads on their
PCBs? I have a feeling most people using PCB are doing so for
hobby/student projects. However, professional-level boards destined
for mass manufacture need this feature. I suppose one could just
create a "testpad" element in PCB to place & hook to every
net. However, since the test pad doesn't appear in the netlist, PCB
will complain every time you refresh the netlist, and it will make DRC
checking a real PITA. Therefore, I have a feeling that any testpad
element needs to be recognized as a special structure by PCB.

Any thoughts? Has anybody tried to place testpads for manufacturing
test?

I haven't done it in PCB, but the way I've handled this issue in a commercial environment with some commercial tools is to create a test point element which has 1 pin on the symbol and the footprint is a single round pad. Then put the test points/pads in the schematic.

This follows my general principle of "if it goes on the board, it goes on the schematic". Also it has the nice benefit of you can easily write a manufacturing rule checker that verifies that you have a test pad on every single net. With the commercial tool I mentioned, I ended up writing a small utility to go with it that gave an in circuit test (ICT) coverage report that listed the total # of nodes in the design, total number covered by test points, and a percent coverage. It also told you what nodes (by name and by what other components connected to the node) did not have test pads. This made it easy to fix up the schematics where there were missing test pads.

It is a bit of a pain, but if you want to reliably get 100% coverage of nodes, I think this is about the only way to go. Using vias can be dangerous because when doing a minor board revision you might constrain yourself to not move any test pads but not moving any vias might be harder (both to deal with and to remember which ones you can't move)

-Dan