Re: gEDA-user: Test pads in PCB

[Dan McMahill <dan@xxxxxxxxxxxx>]

Stuart Brorson wrote:
> Dan,
>
> Just a quick commnet.
>
>
> > This follows my general principle of "if it goes on the board, it goes 
> > on the schematic".  
>
>
> This sounds good in theory, but in practice I see two issues:
>
> 1.  Test points on every net clutters the schematic.

Make the symbol small.  Its not great, but its really not that bad
(speaking from experience on a fairly large RF board with about 700
components).

> 2.  This doesn't correspond to ordinary practice in the places where
> I've worked.  Everywhere I've worked the layout guy did the testpads
> & I didn't have to worry about it, much less change the schematic.
> Then, the manufacturing engineers got the test point position info
> from him, and created the test fixtures/flying probe program files.
> It was transparent to the designers.

How does the layout person ensure that he/she got all of the nodes?

I can't recall since its been a few years now.  Once you have the x-y
positions for all the test points how do you create the actual test
vectors?  I just can't remember if this was based on just doing some
automated thing on a known good board or if a test engineer sat down
with the schematics and did something else.

> Of course, I can imagine that putting/not putting testpoints on
> schematics is a religious issue. . . . .

indeed.

> Anyway, these reasons suggest that PCB be capable of handling test
> pads independently of the schematic.  I agree they shouldn't be vias.
> Rather, they are analogous to vias in that they  are layout specific
> structures which PCB could/should support someday.  Maybe I can look
> at doing it myself someday . . . .

What do you think of this.  Add a gnetlist option which adds a testpad
to every node?  Now its not in the schematic, but we're enforcing the
existance connectivity of the test pads?

For that matter, maybe also add a feature to PCB which says "test pad
me" and it adds test pads to the netlist.  I guess you'd want the 
ability to control the size, perhaps on a pad by pad basis.  I guess to 
start with adding automatically to the database would be good.  This 
shouldn't be hard to implement either.

I really feel that without test pads being included in the connectivity
database, you don't have much chance of getting them all.

Seems like having both a gnetlist option and a pcb option would give the
most flexibility for using pcb and also if you use gschem to drive a
different layout tool.

-Dan