Re: gEDA-user: Test pads in PCB

[Marvin Dickens <marvindickens@xxxxxxxxxxxxx>]

Hal2000 wrote:
> Stuart Brorson wrote:
>
> > I am very pleased to see how much intelligent discussion my little
> > comments have sparked.  This is a very educational thread.
> >
> >  
> >
> > > Hopefully I'm not putting words in Stuarts mouth, but we're really 
> > > talking about 2 different things in this thread.  Some of the 
> > > comments here are related to testing a bare board (no components 
> > > soldered down yet).  In that case, the component pads are probably 
> > > sufficient.
> > >
> > > The 2nd case, which I think is the one Stuart was initially asking 
> > > about, is for automated testing of a board which has been already 
> > > assembled.  In that case, you really do want test pads on all the 
> > > nodes and preferably on one side of the board.  We used to do that 
> > > at a place I worked and it was pretty cool.  They'd stick a fully 
> > > assembled analog/mixed signal board into the tester and catch nearly 
> > > all of the boards with manufacturing (placement/soldering) defects.
> > >   
> >
> > Thanks, Dan.  I am indeed talking about testing fully assembled
> > boards, not raw PCBs.  That's why probing the component pads isn't
> > possible or applicable.
> >
> > Stuart
> >
> >  
> Analog or digital?  If digital, you could use boundary scan - if your 
> parts are jtag.  What about some level of in circuit tests (ICT), 
> followed by system checkout at run-time via diagnostics?
>
> Not sure about analog designs though - not enough experience there.  
> But you could specify bed of nails tests to verify that the components 
> are correct value, and indeed soldered in place.
>
> I've seen both ends of the spectrum regarding board testing.  At one 
> employer we tested all the boards on a teradyne bed of nails machine.  
> Worked really well.  They only do this early on in the production 
> phase - once the machines are programmed correctly, and the soldering 
> profiles are correct, these things generally work 98% of the time.  If 
> you are using a schlock house, then I suppose your mileage will vary 
> :-) Following this phase, board failures are found in functional 
> in-system tests.  Those that fail go back to the teradyne for debug.
>
> Where I work today - they have 0 test coverage from the board house, 
> and we pay dearly for lousy workmanship.  Somehow the management 
> doesn't see it that way - but that's a whole other story.
>
> gene
At work, we are a mixed bag:

(1.)  JTAG for Boundary scanning, debugging  and code loading. 
(2.) A Huntron DSI700 with a Tracker 2000 for everything else.

The Huntron is a pain, but a bed of nails machine, not to mention the
associated tooling expense is beyond our financial reach. As far as the
Huntron equipment goes, we purchased it back around 1993 and it has
paid for itself thousands of times over.

Also, we are able to store signatures of components and circuits using
the Huntron software which lets us average the signatures and automate
testing proceedures (At least, up to a point).

FWIW, these days you can pick up a Tracker 2000 and a DSI 700 for less
than $ 750.00. Also, Huntron manufactures a unit that uses a flying head
with a test probe attached to it for less than 5K (We are looking at buying
one...).

If you need bed of nails capability, but can't afford it, something like 
this
is an inexpensive option (Relative to a bed of nails...).


Best

Marvin