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Re: gEDA-user: Test pads in PCB


That's why I raise the issue of testpads in PCB.  At work I have a
board (my responsibility, but not my design -- ugh!)

same here - I completely agree

with a dismal
yeild. The raw PCBs go through inspection at the assembler OK as far
as I can tell. Since it has no test pads the vendor can't test it
once it's stuffed. They just send us the stuffed boards, and we do functional test on a test platform which is a mock-up of our system.
A good percentage of the boards fail. The failure mode is that the
system acts flakey when this board is installed. If components would
just burn up I could identify the problem. However, the boards look
fine, and all connections which I have buzzed out are good.

One clue: When I stress or flex a failing board in the test system, I
can often make it work (until I release the board). This suggests
cracked vias, ripped internal traces, or SMT passives with
microcracks. All of these are hard to find visually. However, if the
original designer had testpadded the board, we'd be able to reject
these boards at the assembler.

Either your manufacturer has a problem or your design has a mechanical problem. You didn't say if your card is wave soldered, IRed or both. If waved, then it is possible that you have components too high that shadow others causing too little solder to hit the component. If IR, placement is less of an issue, but thermal profile is. Maybe you need to examine that. Also, on IR stuff (like surface mount), the stencil may not be placing sufficient solder on the pads.

Another thought - let's say the manufacturing is good, but the layers of your cards are poorly registered. Those vias connecting layers may not be doing the job since when drilled, the connection is getting lost. This is where electrical test on bare boards really pays off. It's also cheaper than ICT fully stuffed cards.

FYI A bed of nails won't necessarily find poor soldering. We also have poor soldering issue and uncovered them when thermally cycling the board from -40C to +74C. The thermal stress was enough to break a lousy solder joint (too little solder).

In production, you probably want to attain a level of confidence in your design and manufacturing such that ICT is not needed on every single board.

gene