Here is the partial output from Cadence Verilog-XL
Compiling source file "test_case.v"
Highest level modules:
test
At 1 value is 0000000000
At 2 value is 00000xxxxx
At 3 value is 1111111111
At 4 value is 00000xxxxx
At 5 value is 0000000000
At 6 value is 00xxxxxxxx
L13 "test_case.v": $finish at simulation time 7
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.0 secs to compile + 0.0 secs to link + 0.1 secs in simulation
End of Tool: VERILOG-XL 05.30.001-p Jan 20, 2007 16:54:48
Regards,
Kyle
________________________________
From: geda-user-bounces@xxxxxxxxxxxxxx on behalf of Stephen Williams
Sent: Fri 1/19/2007 12:20 PM
To: geda-dev; geda-user@xxxxxxxx
Subject: gEDA-user: Need a Verilog test run
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Hi all,
There is a bug report (pr1632861) is the Icarus Verilog bugs database
that is making claims about how padding is done in a certain case. the
poster claims that Icarus Verilog is getting it wrong and makes some
reasonable points.
I would like to see some other tools run this program so that I can
see what the big names think. Of particular interest is the second
output. Icarus Verilog prints xxxxxxxxxx, but the poster makes the
argument that it should be 00000xxxxx.
module test;
reg[9:0] tst;
initial begin
#1 tst = 0;
// This should set the register to 10'b00000xxxxx!
#1 tst = 5'hxx;
#1 tst = 10'h3ff;
#1 tst = 10'b00000xxxxx;
#1 tst = 0;
#1 tst = 8'hxx;
#1 tst = 0;
$finish;
end
always @(tst) begin
$display("At %0t value is %b", $time, tst);
end
endmodule
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com <http://www.icarus.com/> and lines to code before I sleep,
http://www.picturel.com <http://www.picturel.com/> And lines to code before I sleep."
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