gEDA-user: Need a Verilog test run

[Stephen Williams <steve@xxxxxxxxxx>]

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Hi all,

There is a bug report (pr1632861) is the Icarus Verilog bugs database
that is making claims about how padding is done in a certain case. the
poster claims that Icarus Verilog is getting it wrong and makes some
reasonable points.

I would like to see some other tools run this program so that I can
see what the big names think. Of particular interest is the second
output. Icarus Verilog prints xxxxxxxxxx, but the poster makes the
argument that it should be 00000xxxxx.

module test;
  reg[9:0] tst;

  initial begin
    #1 tst = 0;
    // This should set the register to 10'b00000xxxxx!
    #1 tst = 5'hxx;
    #1 tst = 10'h3ff;
    #1 tst = 10'b00000xxxxx;
    #1 tst = 0;
    #1 tst = 8'hxx;
    #1 tst = 0;
    $finish;
  end

  always @(tst) begin
    $display("At %0t value is %b", $time, tst);
  end
endmodule


- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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